1. Field of the Invention
The present invention relates to color imaging and, more particularly, to color separation in an active pixel MOS imaging array using the differences in absorption length in silicon of light of different wavelengths. An active pixel imaging array in accordance with the present invention reduces color aliasing artifacts in digital images by using a triple-well structure to ensure that each pixel sensor in the array measures each of the three primary colors (R-G-B) in the same location.
2. Description of the Related Art
Relevant prior art of which the inventor is aware may be generally categorized as follows: stacked photodiodes as color sensors, imaging arrays with stacked sensors, and other color imaging array approaches.
The first category includes non-imaging devices for measuring the color of light. These devices have been built with a variety of technologies that depend upon the variation of photon absorption depth with wavelength. Examples are disclosed in U.S. Pat. No. 4,011,016, titled "Semiconductor Radiation Wavelength Detector" and U.S. Pat. No. 4,309,604, titled "Apparatus for Sensing the Wavelength and Intensity of Light." Neither patent discloses either a structure for a three-color integrated circuit color sensor or an imaging array.
The second category includes CCD devices with multiple buried channels for accumulating and shifting photocharges. These devices are difficult and expensive to manufacture and have not been practical for three-color applications. U.S. Pat. No. 4,613,895, titled "Color Responsive Imaging Device Employing Wavelength Dependent Semiconductor Optical Absorption" discloses an example. This category also includes devices that use layers of thin-film photosensitive materials applied on top of an imager integrated circuit. Examples of this technology are disclosed in U.S. Pat. No. 4,677,289, titled "Color Sensor" and U.S. Pat. No. 4,651,001, titled "Visible/Infrared Imaging Device with Stacked Cell Structure." These structures are also difficult and expensive to make, and have not become practical.
The third category includes color imaging integrated circuits that use a color filter mosaic to select different wavelength bands at different photosensor locations. U.S. Pat. No. 3,971,065, titled "Color Imaging Array", discloses an example of this technology.
As discussed by Parulski et al., "Enabling Technologies for Family of Digital Cameras", 156/SPIE Vo. 2654, 1996, one pixel mosaic pattern commonly utilized in digital cameras is the Bayer color filter array (CFA) pattern. Shown in FIG. 1, the Bayer CFA has 50% green pixels arranged in a checkerboard and alternating lines of red and blue pixels to fill in the remainder of the pattern.
As shown in FIG. 2, the Bayer CFA pattern results in a diamond-shaped Nyquist domain for green and smaller, rectangular-shaped Nyquist domains for red and blue. The human eye is more sensitive to high spatial frequencies in luminance than in chrominance, and luminance is composed primarily of green light. Therefore, since the Bayer CFA provides the same Nyquist frequency for the horizontal and vertical spatial frequencies as a monochrome imager, it improves the perceived sharpness of the digital image.
These mosaic approaches are known in the art to be associated with severe color aliasing problems due to the fact that the sensors are small compared to their spacing, so that they locally sample the image signal, and that the sensors for the different colors are in different locations, so that the samples do not align between colors. Image frequency components outside of the Nyquist domain are aliased into the sampled image with little attenuation and with little correlation between the colors.
Accordingly, it is an object of the present invention to provide a color imaging array in which three color bands are measured with detectors each in the same location, with sensitive areas that are not very small compared to their spacing, such that aliased image components are attenuated, and such that the color samples are aligned between colors.
It is a further object of the present invention to provide an active pixel color imaging array that can be fabricated in a standard modern CMOS memory process.
Referring to FIG. 3, many modern CMOS integrated circuit fabrication processes use a "twin well" or "twin tub" structure in which a P well region 10 and an N well region 12 of doping density approximately 10.sup.17 atoms/cm.sup.2 are used as regions within which to make N-channel and P-channel transistors, respectively. The substrate material 14 is typically a more lightly doped P-type silicon (10.sup.15 atoms/cm.sup.2), so the P well 10 is not isolated from the substrate 14. The N-channel FET 16 formed in the P well 10 includes N+ normal source/drain diffusions 18 at a dopant concentration of &gt;10.sup.18 atoms/cm.sup.2 and N-type shallow lightly doped drain (LDD) regions 20 at a concentration of approximately 10.sup.18 atoms/cm.sup.2. The P-channel FET 22 formed in the N well region 12 is similarly constructed using normal P+ source/drain regions 24 and shallow LDD regions 26 of similar dopant concentrations.
Referring to FIG. 4, in improved modern processes, known as "triple well", an additional deep N isolation well 28 is used to provide junction isolation of the P well 10 from the P substrate 14. The N isolation well 28 dopant density (10.sup.16 atoms/cc) is intermediate between the P substrate 14 and P well 10 dopant densities (10.sup.15 atoms/cc and 10.sup.17 atoms/cc, respectively). U.S. Pat. No. 5,397,734, titled "Method of Fabricating a Semiconductor Device Having a Triple Well Structure", discloses an example of triple well technology.
Triple well processes are becoming popular and economical for manufacturing MOS memory (DRAM) devices, since they provide effective isolation of dynamic charge storage nodes from stray minority carriers that may be diffusing through the substrate.